Electronic – How to assign the same value to a bus in Xilinx ISE (Schematic)
isexilinx
How to set all the bits for example in bus(7:0) to the value in net0?
Best Answer
Since net0 is just a single wire you cannot directly attach it to the bus(7:0) because it would logically short all the bus lines together. So to be able to do what you want you will need to use a series of eight buffers. The inputs of all the buffers you wire to net0. Then the outputs of the buffer wire individually to bus(7), bus(6) .... bus(0).
Do note that this brings up a much bigger question here. You are not allowed to create tri-state busses inside most FPGAs. This means that the idea to assign the net0 value to the whole bus does not make much sense. If indeed that is really really intended then just purge the bus(7:0) net entirely and replace it with the net0 wire.
Long answer: I could tell you, but then I'd be wrong. I've been using Xilinx tools for the past 15+ years and every time they come out with a new version (or even a new service pack) things change. Sometimes even just changing various XST/MAP/PAR options will cause new files to be generated. So even if I did give you a list it would likely be out of date or just wrong.
I've created my own makefiles for building my FPGA's (I'm not using ISE's GUI environment), and it's fairly well documented what the input files to the various tools are (XST, MAP, etc). Everything else is not required and thus doesn't need to be checked into the source control system. My makefiles have a "make clean" option that removes all of the extra files. So when Xilinx releases a new version I simply recompile and the "make clean". Any file that remains (and isn't obviously something I need) is considered to be junk, and I add those files to the "make clean" list of things to delete.
It sounds like you figured out your problem, but you can indeed set a custom compilation order in ISE. For example, see this link: Setting a Custom Compilation Order (part of ISE help).
Best Answer
Since net0 is just a single wire you cannot directly attach it to the bus(7:0) because it would logically short all the bus lines together. So to be able to do what you want you will need to use a series of eight buffers. The inputs of all the buffers you wire to net0. Then the outputs of the buffer wire individually to bus(7), bus(6) .... bus(0).
Do note that this brings up a much bigger question here. You are not allowed to create tri-state busses inside most FPGAs. This means that the idea to assign the net0 value to the whole bus does not make much sense. If indeed that is really really intended then just purge the bus(7:0) net entirely and replace it with the net0 wire.