I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some connections have "BUF"s and some don't. I read the documentation (Page 72 of this pdf) and it just says "This element is not necessary and is removed by the partitioning software (MAP).". So if it isn't necessary what is the purpose of adding them to the schematic?
Electronic – the purpose of a “BUF” in Xilinx ISE schematic
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Best Answer
One purpose on the CPLD schematic is that it allows two nets with different names to be tied together.