I want to define an
add module which has a modified parameter in my declaration of the new instance but it doesn't go well.
It is in Verilog. I want to define an instance of this module:
module add #(parameter wd=1) (input wire [wd-1:0] a,b, output wire [wd-1:0] o); assign o = a + b; endmodule
I tried this line but I get an error:
add len_plus_1 #(8)(.a(len),.b(8'h1),.o(lenPlus1));