Electronic – How to define a module with a modified parameter in Verilog

verilog

I want to define an add module which has a modified parameter in my declaration of the new instance but it doesn't go well.

It is in Verilog. I want to define an instance of this module:

module add #(parameter wd=1) (input wire [wd-1:0] a,b, output wire [wd-1:0] o);
   assign o = a + b;
endmodule

I tried this line but I get an error:

 add len_plus_1 #(8)(.a(len),.b(8'h1),.o(lenPlus1));

Best Answer

You've got the order wrong. When using module-instance parameter value assignment (the rather wordy terminology for this method), the syntax is:

module-name #(parameter-assignment) instance-name (module-terminal-list) ;

where the parameter assignment can be by name or by the order of the values. You're already familiar with the module terminal list, so I'll just give the parameter BNF:

parameter-assignment ::= (values-by-name / values-by-order) 
values-by-name ::= .parameter-name(parameter-value)*[, parameter-name(parameter-value)]
values-by-order ::= parameter-value*[, parameter-value]

So your example should be one of the following:

add #(.wd(8)) len_plus_1(.a(len),.b(8'h1),.o(lenPlus1));
add #(8) len_plus_1(.a(len),.b(8'h1),.o(lenPlus1));

The former (named) version is preferred, because it maintains its behavior if you add another parameter.

The following example gives additional options (this is adapted from Figure 9-4 in Verilog HDL: A Guide to Digital Design and Synthesis by Palnitkar)

module bus_master;
  // Note: These could also be ANSI C-style parameter declarations with 
  // module bus_master (#parameter delay1 = 2, delay2 = 3, delay3 = 7);
  parameter delay1 = 2;
  parameter delay2 = 3;
  parameter delay3 = 7;
  ...
  <module internals>
  ...
endmodule

module top;
  // Assignment by name:
  bus_master #(.delay2(4), delay3(8)) b1();
     //delay1 = 2 (default), delay2 = 4, delay3 = 8
  bus_master #(.delay1(1), delay3(6)) b2();
     //delay1 = 1, delay2 = 3 (default), delay3 = 6

  // Assignment by order:
  bus_master #(7, 8, 9) b3();
     //delay1 = 7, delay2 = 8, delay3 = 9
  bus_master #(1, 3, 5) b4();
     //delay1 = 1, delay2 = 3 (default, but by assignment), delay3 = 5
  bus_master #(1, 5) b5();
     //delay1 = 1, delay2 = 5, delay3 = 7 (default)
endmodule

There is also another method which uses the defparam keyword to define the values before instantiation like this:

module top; 
  defparam b6.delay1 = 1;
  bus_master b6();
     //delay1 = 1, delay2 = 3 (default), delay3 = 7 (default)
endmodule;

but that's considered poor style (though personally, I'd prefer it to the values-by-order syntax).

Related Solutions

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

It seems like you are running into Verilog's Escape identifiers gotcha:

§2.7.1 Escaped identifiers

Escaped identifiers shall start with the backslash character () and end with white space (space, tab, newline). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a nonescaped identifier cpu3.

So not only you need to properly write down escaped port name, but you also need to make sure you don't forget to put a whitespace at the end. For example:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .\ptext[5] (ptext_tb[5]),
                 .\ptext[4] (ptext_tb[4]),
  ...

Hope it helps. Good Luck!

Electronic – Memory modelling and Memory module in Verilog synthesis

I am not sure why you need a special option, the use of memories are pretty standard for use inside modules. Unless you are trying to imply a special low area/power cell similar to a ram.

For a standard memory it is just the same as having multiple regs. memory does not imply RAM the same way reg does not automatically imply flip-flop.

The 'memory.list' is a plain text file which contains the values which you want to load in to the memory, this is not required if you just wanted to reset the memory and have every element at 0.

memory.list should look like :

//Comments are allowed 
1100_1100   // This is first address i.e 8'h00
1010_1010   // This is second address i.e 8'h01
@ 55        // Jump to new address 8'h55
0101_1010   // This is address 8'h55
0110_1001   // This is address 8'h56

The use of the file would then follow :

module  memory();
  reg [7:0] my_memory [0:255];

  initial begin
    $readmemh("memory.list", my_memory);
  end
endmodule

alternatively :

module  memory();
  reg [7:0] my_memory [0:255];
  integer i;

  initial begin
    for( i=0; i<256; i=i+1) //Can be statically unrolled
      my_memory[i] = 8'h00 ;
  end
endmodule

If using as a bank of flip-flops with async-reset:

module  memory(
  input clk,
  input rst_n,
  input [7:0] addr_wr,
  input [7:0] data_wr
);
  reg [7:0] my_memory [0:255];
  integer i;

  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
      for( i=0; i<256; i=i+1) //Can be statically unrolled
        my_memory[i]  <= 8'h00 ;
    end
    else begin
      my_memory[addr_wr] <= data_wr ;
    end
  end
endmodule

Best Answer

Related Solutions

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

Electronic – Memory modelling and Memory module in Verilog synthesis

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