I don't have experience with Quartus, so treat this as general advice.
When working on paths between clock domains, timing tools expand the clocks to the least common multiple of their periods and select the closest pair of edges.
For paths from a 36 MHz clock (27.777 ns) to a 100 MHz clock (10 ns), if I did my quick calculations correctly, the closest pair of rising edges is 138.888 ns on the source clock and 140 ns on the destination clock. That's effectively a 900 MHz constraint for those paths! Depending on rounding (or for clocks with no relationship), it could come out worse than that.
There are at least three ways to write constraints for this structure. I am going to call the clocks fast_clk
and slow_clk
as I think that's clearer for illustration.
Option 1: disable timing with set_false_path
The easiest solution is to use set_false_path
to disable timing between the clocks:
set_false_path -from [get_clocks fast_clk] -to [get_clocks slow_clk]
set_false_path -from [get_clocks slow_clk] -to [get_clocks fast_clk]
This is not strictly correct, since there are timing requirements for the synchronizer to work correctly. If the physical implementation delays the data too much relative to the control signal, then the synchronizer will not work. However, since there isn't any logic on the path, it's unlikely that the timing constraint will be violated. set_false_path
is commonly used for this kind of structure, even in ASICs, where the effort vs. risk tradeoff for low-probability failures is more cautious than for FPGAs.
Option 2: relax the constraint with set_multicycle_path
You can allow additional time for certain paths with set_multicycle_path
. It is more common to use multicycle paths with closely related clocks (e.g. interacting 1X and 2X clocks), but it will work here if the tool supports it sufficiently.
set_multicycle_path 2 -from [get_clocks slow_clk] -to [get_clocks fast_clk] -end -setup
set_multicycle_path 1 -from [get_clocks slow_clk] -to [get_clocks fast_clk] -end -hold
The default edge relationship for setup is single cycle, i.e. set_multicycle_path 1
. These commands allow one more cycle of the endpoint clock (-end
) for setup paths. The -hold
adjustment with a number one less than the setup constraint is almost always needed when setting multi cycle paths, for more see below.
To constrain paths in the other direction similarly (relaxing the constraint by one period of the faster clock), change -end
to -start
:
set_multicycle_path 2 -from [get_clocks fast_clk] -to [get_clocks slow_clk] -start -setup
set_multicycle_path 1 -from [get_clocks fast_clk] -to [get_clocks slow_clk] -start -hold
Option 3: specify requirement directly with set_max_delay
This is similar to the effect of set_multicycle_path
but saves having to think through the edge relationships and the effect on hold constraints.
set_max_delay 10 -from [get_clocks fast_clk] -to [get_clocks slow_clk]
set_max_delay 10 -from [get_clocks slow_clk] -to [get_clocks fast_clk]
You may want to pair this with set_min_delay
for hold checks, or leave the default hold check in place. You may also be able to do set_false_path -hold
to disable hold checks, if your tool supports it.
Gory details of edge selection for multi-cycle paths
To understand the hold adjustment that gets paired with each setup adjustment, consider this simple example with a 3:2 relationship. Each digit represents a rising clock edge:
1 2 3
4 5 6 7
The default setup check uses edges 2 and 6. The default hold check uses edges 1 and 4.
Applying a multi-cycle constraint of 2 with -end
adjusts the default setup and hold checks to use the next edge after what they were originally using, meaning the setup check now uses edges 2 and 7 and the hold check uses edges 1 and 5. For two clocks at the same frequency, this adjustment makes sense — each data launch corresponds with one data capture, and if the capture edge is moved out by one, the hold check should also move out by one. This kind of constraint might make sense for two branches of a single clock if one of the branches has a large delay. However, for the situation here, a hold check using edges 1 and 5 isn't desirable, since the only way to fix it is to add an entire clock cycle of delay on the path.
The multi-cycle hold constraint of 1 (for hold, the default is 0) adjusts the edge of the destination clock uesd for hold checks backwards by one edge. The combination of 2-cycle setup MCP and 1-cycle hold MCP constraints will result in a setup check using edges 2 and 7, and a hold check using edges 1 and 4.
Best Answer
What you have now is a three stage synchroniser running in the fast clock domain, so the reset output isn't a suitable synchronised reset for the core. Change the always block to be
@(posedge clock)
. But there are other considerations:For resets, you need to specify precisely how the reset should appear in the slow clock domain:
Once you know the answers, you can design the reset circuitry. If you need to accept short input pulses, you need to use asynchronous clear on the first flop, and have it self set once the reset is delivered. The first flop is followed by the synchronisation chain.
On the clock divider
You don't mention which device you are using - if this is a hardware (FPGA - judging from the warnings) rather than theoretical exercise then I would advise you to use the technologies built into the device to do the clock division. In an FPGA instantiate a fPLL/PLL to output the lower speed clock, rather than inferring it from logic. This is still applicable for the ratio you have here: save yourself the 14 bit counter and use the built in. You can then easily add other derived clocks later, and take advantage of direct connections to the (skew-controlled) clock distribution network. For simulation, you can easily mock out the pll/replace it with a separate clock.
However what you might want is a gated clock enable (with the same period) rather than a new clock - it depends if the slow core can meet timing in the fast clock domain. I'd do this if the core is small (so power isn't an issue) trivial (so meets timing) and the clock change was only to meet some external bus requirements. This may make moving data between the core and the rest of the design easier.
If you were to use this inferred clock divider, there's no need to wire up reset logic for it. It will work and simulate fine if you initialise countCLK to zero in the Verilog so it has that value out of configuration.