I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
Electronic – How to find the critical path delay of a big combinational block
digital-logicverilog
digital-logicverilog
I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
Best Answer
If it's a combinatorial multiplier you won't need to clock it.
But the easiest form of timing constraint is clock period, so instantiate the multiplier with registers on every input and output, all clocked from the same clock. Specify your required clock frequency, synthesise the design, and run static timing analysis (STA) on the result.
The timing analysis report ought to indicate the critical path, and report its speed, indicating whether or not your speed goal was met. It should also indicate the delay introduced by each logic element and interconnection on the critical path, to help you decide how to improve its speed if necessary.
After synthesis, this report is an estimate (usually a pretty good one). For completely accurate results, you would need to place and route the synthesised design, and run STA on the routed design.