Verilog – Radix-4 Booth’s Multiplier Code Error

digital-logicmodelsimmultiplierverilog

I wrote the code for radix 4 booth's multiplier. But, I am getting 2 errors. I am not able to solve it.
Could you please help?
The errors are:

Error: C:/modelsim_dlx64_2021.1/examples/assignment/booth.v(14): (vlog-2110) Illegal reference to net "B1".

Error: C:/modelsim_dlx64_2021.1/examples/assignment/booth.v(35): Range must be bounded by constant expressions.

CODE

module booth_mul #(parameter N=8,M=8,logN=4)(clk,start,rst,A,B,y,done);
input clk,rst,start;
input [N-1:0]A;
input [M-1:0]B;
wire [M:0]B1;
output reg done;
output reg [N+M-1:0]y;
reg [logN-1:0]count;
reg [N+M+2:0]acc;

always@(posedge clk)

begin
B1={B,1'b0};
if(rst==1'b1)
begin
    
    acc = {N+M+3{1'b0}};
    count = {logN{1'b0}};
    done=1'b0;
end
else
begin
    if(start==1'b0)
    begin
        acc[M:0] = B1;
        acc[N+M+2:M+1] = {N+2{1'b0}};
        count = {logN{1'b0}};
        done=1'b0;
    end
    else
    begin
        if(count<M)
        begin
            case(acc[count+2:count])
            3'b000 : acc = acc;
            3'b001 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + {A[N-1],A[N-1],A};
            3'b010 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + {A[N-1],A[N-1],A};
            3'b011 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + {A[N-1],A,1'b0};
            3'b100 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + ~{A[N-1],A,1'b0} + 1'b1;
            3'b101 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + ~{A[N-1],A[N-1],A} + 1'b1;
            3'b110 : acc[N+M+2:M+1]<=acc[N+M+2:M+1] + ~{A[N-1],A[N-1],A} + 1'b1;
            3'b111 : acc = acc;
            endcase
        
            acc = {acc[N+M],acc[N+M:1],acc[N+M:2]};
            count = count + 2;
            done = 1'b0;
        end
    
    else
    begin
        count = count;
        done = 1'b1;
        y=acc[N+M-1:0];
        
    end
    end
end
end
endmodule

Best Answer

You can't keep both the indices of the range a variable, while indexing an array in Verilog. At least one index has to be a constant for the Synthesiser to be able to resolve the expression.

Verilog has a standard syntax to address your intention:

acc [count +: 3]

This is called part-selecting, where 3 signifies no. of bits of acc being addressed, and the lower index of the range is count.

For eg: if count is 4, then acc [count +: 3] means acc [6 : 4]

Related Topic