Electronic – SDC constraints for two flop sychronizer

cdcconstraintssynthesistiming-analysisvlsi

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer.
between "dat driving by aclk to bdat1 driving by bclk"
Note: aclk and bclk are not the same, also question for what if same too?

Is it false path?

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Following is SDC constraints file I have used,

# Input ports
# -----------------------------------------------------------------------------
set_input_delay $ACLK_IN_DELAY  -clock $SCLK [get_ports dat ]  

set_input_delay $V_CLK_1_IN_DELAY     -clock $V_CLK_1    [get_ports srst_ni]  
set_input_delay $V_CLK_1_IN_DELAY     -clock $V_CLK_1    [get_ports drst_ni]  

# Output ports
# -----------------------------------------------------------------------------
set_output_delay $BCLK_OUT_DELAY  -clock $DCLK [get_ports bdat2]

Best Answer

Since its source clock is aclk and target clock is bclk, adat should be the only false path here. Other paths are valid and don't require any special constraint.

The false path can be defined to the data input pin of the second register (the one between adat and bdat1). I don't know how your tool treats the register names, but I used Synopsys' naming convention in the following example.

set_false_path -to bdat1_reg/D

There is a second way to define this false path. If the clocks are defined asynchronous to each other, adat will be false path automatically. I assume ACLK and BCLK are previously defined clocks.

set_clock_groups -asynchronous -group ACLK -group BCLK
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