I'm designing a board for a hobby project where I am using a lattice machxo2 cpld as a system interconnect.
The cpld needs to be clocked at 80-100MHz, and because I sprung for a cheaper cpld, it has no on board PLLs. The easiest way for me to clock it is to use a programmable clock from my main mcu (Atmel SAM4S) to clock the cpld (with a pcb trace of about 3cm).
Because the signal is 100MHz, the slew rate will have to be fairly high, and I'm expecting a lot of ringing. Can I reduce the ringing by adding a small resistor to the output pin of the MCU (10-100 Ohm) and a small cap to ground on the clock line (10-100pF)? According to my back of the envelope math, these values will force the rise/fall time to be around 1ns.
simulate this circuit – Schematic created using CircuitLab
Will this approach work? Is it common practice? I'm coming from a CS background, so my knowledge is a little shaky.
Thanks.
Best Answer
I'm assuming this your clock source is a dedicated clock output in on the MCU, so it should be able to handle the slew rates just fine (assuming it is designed for these frequencies). One possible source of ringing might be transmission line effects (or any bad layout issues).
A general rule of thumb is that if your wavelength is greater than 10x the trace length, you can ignore transmission line effects.
A square wave is composed of odd harmonics, so let's take the 5th harmonic at 500MHz. With 2/3 speed of light propagation, the wavelength is ~.4m. This is more than 10x your trace length, so you can likely ignore these. However, considering the 7th harmonic and it's a different story. Now transmission line effects do matter.
The usual technique for getting around transmission line effects is to use matched impedance resistors (not an RC filter). This is relatively easy when you have a cable with a rated characteristic impedance; it's harder for a trace, and is dependent on geometry. For example, I've linked the way to calculate the characteristic impedance of a microstrip. You usually can find calculators online which handle various common geometries.
Since your clock trace will always originate from the MCU, you can place this termination resistor in series with the trace near the clock out pin (again following the rule of thumb of <10x the trace length).
Another way you could gauge how much you need to worry about transmission line effects is with this online transmission line simulator (shameless plug). At the 11th harmonic, the amplitude has decreased to 1/11th the amplitude of the fundamental frequency, so you can use the inverse of the 11th harmonic (909ps) as the rise and fall time. Pick a badly matched R1 (termination resistor) and see if the ringing level exceeds ~10% (or whatever tolerance you deem is acceptable for your application) to determine if you need to worry about termination.
edit:
The reason an RC circuit isn't used is because it doesn't solve the transmission line problem. To illustrate this, I've created two circuits:
Filter near CPLD
The first circuit puts the RC filter at the receiving end of the transmission line (near the CPLD).
I simulated this using various values for C1. R1 and R2 were intentionally chosen to not match the characteristic impedance.
C1 = 100pF (\$f_{-3dB} = 1590 MHz\$)
C1 = 330pF (\$f_{-3dB} = 482 MHz\$)
C1 = 500pF (\$f_{-3dB} = 318 MHz\$)
As you can see none of these are effective at reducing overshoot; they just turn your nice defined square wave into garbage.
Filter near MCU
C1 = 100pF (\$f_{-3dB} = 1590 MHz\$)
C1 = 330pF (\$f_{-3dB} = 482 MHz\$)
C1 = 500pF (\$f_{-3dB} = 318 MHz\$)
It appears like this is an effective technique, however if you look at the 500pF case, the clock edge is becoming more and more like an exponential. Eventually it will decrease the output amplitude, which is not good.
You could build a higher-order filter which is much better at removing just the frequencies above the transmission line limit, but there are problems: