Electronic – the difference between reg and wire after synthesizing

synthesisverilog

Assuming i have these two codes:

module wire_example( a, b, y);
  input a, b;
  output y;

  wire a, b, y;

  assign y = a & b;

endmodule

and the second one is:

module reg_combo_example( a, b, y);
input a, b;
output y;

reg   y;
wire a, b;

always @ ( a or b)
begin   
  y = a & b;
end

endmodule

my question is what is the difference in the net list, both of them will have an gate, but will the module with reg y will have a flip flop or a latch to hold the data while wire y won't have any latch?

Best Answer

Neither of your examples will contain any latches or flip-flops. The always block in your second example is combinational, not sequential (if it were to synthesize a latch, what clock would control that latch?). You have to use a reg type for y simply because it appears on the left side of an assignment statement inside an always block. Many people consider this a disadvantage of Verilog, which is hard to argue with. In VHDL, a signal type would be used instead of both wire and reg, removing the confusion.

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