Assuming i have these two codes:
module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule
and the second one is:
module reg_combo_example( a, b, y); input a, b; output y; reg y; wire a, b; always @ ( a or b) begin y = a & b; end endmodule
my question is what is the difference in the net list, both of them will have an gate, but will the module with
reg y will have a flip flop or a latch to hold the data while
wire y won't have any latch?