Why is having a 2 stage flip-flop desirable? Are there advantages of having a master-slave compared to a one stage JK flip flop?
Flip-Flop – Purpose of a Master-Slave Flip-Flop
flipflop
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The master-slave arrangement doesn't strictly solve the metastability issue, AFAICT. It is commonly used to cross over between different clock domains of synchronous logic, but I don't quite see what improvement it does on purely asynchronous input (the slave gets a clear state, but it may be derived of a metastable transition anyway). It could simply be an incomplete description, as you could add a hysteresis function by combining the outputs of the two registers.
As for the differences between SR, JK, D or even T flip-flops, it tends to boil down to which inputs are asynchronous. The simplest SR latches do not toggle with S=R=1, but simply keep whichever state was kept last (or in the worst case, oscillate with a gate delay), that's the race. The JK, on the other hand, will transition on the clock edge - synchronous behaviour. It is thus their nature that a T register can only be synchronous, and an asynchronous D latch is transparent while latching. The SR register you describe doesn't have the T function, which can be useful depending on the function. For instance, a ripple counter can be described purely with T registers. Simply put, the JK gives you a complete set of operations (set, clear, toggle, and no-op) without costing an extra control line.
In synchronous logic, we frequently use wide sets of registers to implement a larger function. It doesn't strictly matter there if we use D, T, JK or whatever registers, as we can just redesign the logic function that drives them to include feedback (unless we need to build that logic - i.e. in 74 family logic). That's why FPGAs and such tend to have only D registers in their schematic representations. What does matter is that the register itself introduces the synchronous operation - steady state until the next clock. This allows combining plenty of side-by-side registers or ones with feedback functions.
As for the choice between delayed-pulse and clock-synchronous logic, it's not an automatic one. Some early computers (f.e. PDP-1) and even some highly energy efficient ones (f.e. GreenArrays) use the delayed-pulse design, and it is in fact comparable to a pipelined design in synchronous logic. The Carry-Save adder demonstrates the crucial difference - it's a pipelined design where you actually don't have a known value, not even intermediate, until the pulse from the last new value to enter has come out the other end. If you know at the logic design stage repeated accumulation but only the final sum is used, it may be the best choice. Meanwhile, FPGAs are typically designed with only a few clock nets and therefore do not adapt well to delayed-pulse logic (though it can be approximated with clock gating).
I hope this is more helpful than further confusing... interesting questions!
Master-slave just a way of combining two gated or level triggered latches together to form an edge-triggered flip flop. A master-slave D flip flop is just one way that you can build a D flip flop.
The idea behind a master-slave flip flop is that you can connect two latches back to back so the 'master' latch will update while the clock is low and the slave latch will update while the clock is high. In this instance, when the clock transitions from low to high, the current state at the input of the master flip-flop is captured and propagated to the output. This functionality forms a D flip-flop.
However, master-slave is not really the only way to build a D flip-flop. It is possible to build both dynamic gates that use capacitance to hold the value during the clock transition, allowing the gate to be much smaller and simpler. It is also possible to build the same functionality with some inverters and transmission gates. It depends on what level of the design you are working at. If all you haveis logic gates, you probably need to build a master-slave flip-flop. However, if you are working at the transistor level, then you can build something more optimized.
tl;dr: a master-slave flip flop IS a D type flip-flop, but it is ot the only way to make one.
Best Answer
The problem with simple JK latch is the race condition.
Race condition is that as long as the clock is high, when the propagation delay is less than the pulse period, the output toggles between 0 and 1 if
J=K=1.This is undesirable because the value can be undetermined. Master-Slave configuration of two JK latches eliminates this race problem.
A simple positive edge triggered Master-Slave JK flip-flop consists of two cascaded latches: One negative latch and a positive latch.
Latches are level triggered. When the clock is low, The first latch is in transparent mode the second latch is in hold mode. When the clock is high, The first latch is in hold mode the second latch is in transparent mode. They together act as a positive edge triggered Master-Slave JK flip-flop.
When clock makes transition from 0 --> 1, the first latch moves from transparent to hold mode, while the second latch moves from hold to transparent mode at the same time. i.e., The output of the first latch just before that rising clock moment would be the data sampled by the second latch. This data is available at Q after clock becomes high, because the second latch is now in transparent mode. Once the clock becomes high, changes in the input of the first latch is not reflected anymore at the output Q because it is in hold mode now. In the previous case, when clock is high and J=K=1 , the outputs goes on toggling till the clock goes low. This problem no longer exists in this case.