Verilog – Use Condition from One Clock with Registers from Another, Synchronized Clock

clocktiming-analysisverilogvlsi

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency?

This works as expected in simulation:

`default_nettype none

`timescale 1ns/1ps
module top;

   reg base_clk = 0;
   reg fst_clk = 0;

   reg cond = 1'b0;
   reg [2:0] ctr = 3'd0;
   reg some_reg = 1'b0;

   always #15 base_clk = !base_clk;
   always #5 fst_clk = !fst_clk;

   initial begin
      $dumpfile("top.vcd");
      $dumpvars(0, top);
      #10000 $finish;
   end

   always @(posedge base_clk) begin
      ctr  <= ctr + 1'b1;
      if (ctr == 3'd5)
        cond <= 1'b1;
      else
        cond <= 1'b0;
   end

   always @(posedge fst_clk) begin
      if (cond)
        some_reg <= 1'b1;
   end

endmodule

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Can I assume this will also work when synthesized (in synthesis fst_clk would be generated by a PLL)? In my mind there shouldn't be any issues here since the clocks are synchronized and so I'm not crossing clock domains. Am I correct in thinking this? Or, have I overlooked something and I should only use a condition generated by the same clock.

Best Answer

Since both your clocks are generated by the same PLL, they are synchronous with well known phase relationship. Hence, there is no asynchronous clock domain crossing between the signals driven by base-clk and fast-clk.

When sending data from slow clock to fast clock, as long as the fast clock has sufficiently smaller time period, there should be no risk of data loss. However, these inter-clock paths have to be properly multi-path constrained and ensure that timing is met.

Sending data from fast clock to slow clock is different story. You will get some good insight here

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