Electronic – Verilog: negative value in brackets of vector signal definition

digital-logichdlverilog

I am looking at the code in the following website.

https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf

In their code, they claims something like

input signed [7:-12] c_in;

I am wondering what does the negative mean in here?

module scaled_square ( output reg signed [7:-12] y,
input signed [7:-12] c_in, x,
input [11:0] i,
input start,
input clk, reset );
wire c_ram_wr;
reg c_ram_en, x_ce, mult_sel, y_ce;
reg signed [7:-12] c_out, x_out;
reg signed [7:-12] c_RAM [0:4095];
reg signed [7:-12] operand1, operand2;
parameter [1:0] step1 = 2'b00, step2 = 2'b01, step3 = 2'b10;
reg [1:0] current_state, next_state;
assign c_ram_wr = 1'b0;

Best Answer

Example 1

reg [3:0] addr;

The 'addr' variable is a 4-bit vector register made up of addr[3] (the most significant bit), addr[2], addr[1], and addr[0] (the least significant bit).

Example 2

wire [-3:4] d;

The d variable is 8-bit vector net made up of d[-3] (msb), d[-2], d[-1], d[0], d[1], d[2], d[3], d[4] (lsb).

Source: http://verilog.renerta.com/mobile/source/vrg00057.htm

So [7:-12] c_in; would create this array of wires/integers or whatever your creating an array of:

c_in[7]
c_in[6]
c_in[5]
c_in[4]
c_in[3]
c_in[2]
c_in[1]
c_in[0]
c_in[-1]
c_in[-2]
c_in[-3]
c_in[-4]
c_in[-5]
c_in[-6]
c_in[-7]
c_in[-8]
c_in[-9]
c_in[-10]
c_in[-11]
c_in[-12]

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