Digital Logic – Verilog Output is HiZ in Testbench

digital-logicmodelsimverilog

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance)

    module mux2to1_tb();
  reg[1:0] r0,r1;
  reg r2;
  wire[1:0] out;

  initial
  begin
    r0=1;
    r1=3;
    r2=0;
    #10;
    r2=1;
    #10;
  end

  mux tm(r0,r1,r2,out);

endmodule

here is the mux module

module mux(d0,d1,s0,out);
  input[1:0]d0,d1;
  input s0;
  output[1:0] out;
  wire [1:0]w1,w2,w3,w4;

  assign w4[0]=s0;
  assign w4[1]=s0;

  inv2bit M0(w4,w3);
  and2bit M1(d0,w3,w1);
  and2bit M2(d1,w4,w2);
  or2bit M3(w1,w2,out);

endmodule

  /*assign w3= ~w4;
  assign w1= d0&w3;
  assign w2= d1&w4;
  assign out= w1|w2;*/

this is the or module

module or2bit(iA,iB,out);

  input iA,iB;
  output out;

  assign out= iA|iB;

endmodule

this is the inverter module

module inv2bit(i1,out);

input i1;
output out;

  assign out= ~i1;

endmodule

Best Answer

You declared the out signal as a wire in your testbench, and you connected it to the out output port of your mux module. However, the out signal in mux is undriven (it is not connected to anything else). In Verilog, wire signals default to the z value.

In mux you have an undeclared signal named outX. Is this X a typo? In other words, out and outX are two different signals. If you rename outX as out everywhere, the out will be connected.

UPDATE: You have confirmed the X was a typo, and updated the Question accordingly. That problem is solved.

Since you added the inv/and/or module code to the Question, we can see that you try to connect 2-bit signals to 1-bit ports in your submodules. For example: w4[1:0] to i1 in inv2bit. You need to change the port declarations to be 2-bit wide, such as:

input  [1:0] i1;
output [1:0] out;
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