This looks like a homework question, which I won't answer. But here are some pointers:
You cannot represent more states than what you have available -> that means that you will have to go to the next higher state (i.e. 2 FF's for 4 states) or use only one FF per state. (i.e. FF #1 correlates directly to A).
option #1 ( 2 FF's and 4 states) is more economical but you have to make sure that the unused state does n't not get activated and then locks out.
- you might draw this as a 4th state "D" with loops back to itself.
- what is generally considered safe design is that you always have explicit transitions AWAY from the unused state in case it gets activated.
option #2 uses more FF's but cannot have any hidden states.
- it is inherently safer.
- it is known as a "one hot" design and thermometer codes are examples of this.
Your choice of states "A = 00" etc. will make the design simpler or more complicated. SO may want to go with what you decribe or you may want to go with state C = "10". You should look at all possibilities.
The first SM, only uses 0 or 1 as an input because it only has one input variable. They should have used a variable for clarity anyways. You'll notice in the table that it is marked as "x" but not in the diagram.
Actually, the structure of your verilog looks just fine. It's the details that are wrong, in a lot of places. Here are some:
reg [3:1] y2, y1, Y2, Y1
Yes, the missing semicolon throws the compiler off. More to the point, [3:1] tells it that each of these regs is three bits wide, but they're only one bit wide in the planning. Traditionally we use 0 for the least significant bit (such that the binary interpretation has weight 2^n at bit n). The parameter line would thus be [1:0], as it is you extend it to three bits wide.
always @(w,y2,y1)
always @(negedge Resetn, posedge Clock)
The sensitivity list is separated by or, not comma.
case (y2)
A: if (w) Y2 = 0;
Y1 = 1;
else Y2 = 0;
Y1 = 0;
y2 in this case statement only matches one bit in your planning (three in the code, but that made less sense). You can concatenate bits using {y2,y1}; in fact, extending the case to case ({y2,y1,w}) will let you use case matches like {A,1'b0}: and remove the if statements entirely.
Secondly, you are trying to manage groups of statements (both assignments to Y2 and Y1) with if; doing so requires enclosing them with begin and end. Alternatively, you could make a wider assignment such as {Y2,Y1} <= B;, which ends up more readable as it can use your named states.
Thirdly, assignment using = can cause some confusion (it acts more like sequential languages, while <= doesn't modify the meaning of a reg within your always). In this case, it is fine as the block is fully combinatorial and does not depend on its own outputs.
Finally (for the case section), you can simply add more matches. You don't even need a default match, but it's probably convenient to use default to go to state A in this case.
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) //something :/
else //something else :/
Something and something else would be register updates, such as {y2,y1} <= {Y2,Y1};. It is the clock edge sensitivity that turns the regs into flipflops.
Finally, since you should now understand what defines a reg width, why don't you make two bit wide regs named state and next_state to replace {y2,y1} and {Y2,Y1} respectively?
Best Answer
Your instinct is correct - assign labels to the FF outputs, e.g., Q1 and Q2. To form a state table, on the left side, list the the four possible states of Q1, Q2; on the right side, write the values that Q1 and Q2 will assume after the next clock pulse. The table will then contain a complete description of the state machine.