The choice is purely arbitrary. Some flip-flop types can reduce the complexity of your next-state logic. However it is really hard to say which one will be best because you would need to check every flip-flop type with every encoding you could possibly use.
D flip-flops are easy to use because its excitation is exactly the same as the next state.
If you plan to use CPLDs or FPGAs to implement your machine use D flip-flops as they will have a D flip-flop built in. their
At a glance to get your circuit, the wiring seems wrong, in halfclk you had:
dff dff1(clk, reset, d, q, qb);
dff dff2(w1, reset, d1, w2, qb1);
Shouldn't it be (renaming a little bit for clarity):
input clk, reset;
output q1, q2;
wire qb1, qb2;
dff dff1(clk, reset, qb1, q1, qb1);
dff dff2(q1, reset, qb2, q2, qb2);
However a warning: If you use the q output to the clock, a real circuit will add up a significant delay. That's bad for a number of reasons. In some circumstances it's ok though, if you don't care about the phase relationship. If you do care, then look into designing a synchronous counter. Also, for a real circuit, buffer the output from the counter, otherwise if you just pass out q or qb it might see a big load and your counter will (at best) slow down even more.
Best Answer
Your question is actually pretty vague (without having that book in front of me anyway. You could be talking about digital or analog signals). But since you mentioned a flip flop I'll make the assumption that you're asking about taking a digital square wave of frequency N and realizing a square wave of frequency N/x, where x is an arbitrary number.
A d flip flop can be useful in realizing such a circuit especially if you want to divide the frequency by a power of two. The easiest way to visualize this stuff and get going is imagine a single flip flop with an inverter between the q output and d input clocked by the input square wave in question. The q output would change state (toggle) every other clock. In other words you'd be dividing your input signal by two. You could chain multiple flops together and divide by 4, etc.
That's useful if you want to divide by a power of two, but what about something else? Say, 3? Then you could use a counter and a magnitude comparator to drive the input of a flip flop. In this circuit you could have a free running counter with reset. You'd have a comparator that compares the count value to 2 (3-1 since you start counting at zero). A flip flop would register the output of your magnitude comparator. When that output of the comparator is true you'd get a pulse that's one clock period high. You could use the output of the comparator to reset the counter such that every three cycles you get a pulse. The duty cycle of your output signal wouldn't be 50% anymore (assuming the input signal is), but you'd have a signal that's 3 times slower (or whatever you're using as input to the comparator) than input. This can be really useful for enable logic or something where you want to do something every x cycles.
There are other "fancier" ways to divide a digital signal (or realize an "arbitrary" digital signal from an input one) that involve phase locked loops, DCMs, etc. These are frequently found on FPGAs, micros, and ASICs, but since you're asking the question it's 99.9999% certain that you wouldn't be in a position to build one of these, but rather control its parameters such that you get an output signal that meets your requirements.