Electronic – What’s causing a master-slave JK flip flop to get ‘stuck’

Many kinds of latching circuits are prone to starting up in an ill-defined state. In your nor-based RS latch, if on powerup both inputs are low and the gates are assumed to output low, then all the inputs to both gates will be low, so the gates will output high. Then since each gate will have an input high, both will output low, etc.

A nice approach to the problem, if you're allowed to use it, would be to have one of the NOR gates of each latch take three inputs, and wire the extra input from both of them to an "asynchronous reset" signal which will be pulsed high on simulation start-up. Otherwise, it will be necessary to ensure that both of your latches get clocked soon enough after simulation start that the simulator won't squawk at the oscillation.

No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:

• The output of NAND4 will be high.
• The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
• The output of NAND1 is low.
• The output of NAND2 is high, thus S is high, and R keeps low.

The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.