Electronic – why there is a need to define temporary reg and only then assign to the output in verilog

registersystem-verilogverilog

Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear as shown in ASIC.CO.IN:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] tmp;
always @(posedge clk or posedge clr)
begin
   if (clr)
      tmp <= 4’b0000;
   else
      tmp <= tmp + 1’b1;
end
   assign q = tmp;
endmodule

Can I define the output as reg and write the verilog as following?:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] q;
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4’b0000;
   else
      q<= q+ 1’b1;
end

endmodule

As I see this, there is no difference between those two codes, am I wrong?

Best Answer

There is no difference in the two examples you wrote. You can even make is simpler:

module counter (
  input  wire clk, clr,
  output reg [3:0] q
);
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4'b0000;
   else
      q<= q+ 1'b1;
end

endmodule

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Verilog: Pass a vector as a port to a module

The code you showed has a few problems:

You don't show how error_count is declared in the top-level module. If error_count is just declared as wire error_count;, you only have a single bit of your counter connected between the counter module and the lcd module.
You don't show how the counter is updated in the counter module. You could have a bug there that results in the counter never updating. Since it is initialized to 0, you'd always have a 0 output from the counter module.
You don't show any clock input to the counter module. If clock is not connected, error_counter will never be updated.
You say that lcd has a clock input, but you don't show that it actually does, and you don't show any code where it matters.
You don't show how your clock is generated. If there's no clock, the counter won't updated.
You don't show the complete input and output ports to either module. With your coding style it's easy to connect a wrong input to a wrong port. I much prefer to intantiate modules with the syntax like

counter counter1 ( .clk( clock ) , .error_count( error_count ) );

With this style, the order of naming the in's and out's in the instantiation doesn't matter.
You haven't shown any reset signal, but you probably have one. If the reset is stuck in the active state, probably the error_count won't ever increment.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

Related Solutions

Verilog: Pass a vector as a port to a module

Electronic – Verilog asynchronous reads of regs – and design question

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