FET array – logical switch

You are going to need to re-think how you drive the FB180SA10B FET. The VgsTH spec of 4V max is only going to assure you of a measely 250uA of drain current. One would have to guess that if you plan to use a monster FET looking like this:

...that you are planning to put some serious current through the part. For this you really need to be looking at Figure 2 from the data sheet to get an idea of the kind of gate drive voltage that you will really need to drive this FET:

For example if you wanted to operate the part at 20usec pulses of 100A and keep the package junction temperature at a safe level (assuming you heat sink the part properly) maybe you could live with 105 watts of device power dissipation. At 105 watts and 100A of drain current the device would be operating with a Vds of about 1.05 volts. Looking at the above graph you can see that this puts you at a VGS in the range of 6 to 6.5 volts. And you really would do well to increase the drive even more upwards.

There are no 5V logic gates that will provide the kind of drive needed here. If you have to use a 5V supply then you should be looking for a FET driver that has internal boost circuitry to produce a gate drive of 9 or 10 volts.

Also note that these devices have a HUGE gate capacitance. The part is speced with:

To reduce switching losses in the FET you want to swing the gate with fast rise times. Swinging this large capacitance fast requires a FET driver than can source a very respectable amount of current. Few standard logic gates will come close to the requirements for this.

I'm going to post an answer but it's really adding more details to Mario's correct answer and, if he wants to strip my answer of anything I'll just delete this.

A randomly googled MOSFET output (DS) capacitance versus drain voltage: -

It doesn't matter what MOSFET you use, the drain capacitance (\$C_{OSS}\$) at 1V (as per Sergei's table in his question) will increase to something like 4 times that value when the MOSFET is fully on in the triode region. The drain voltage is 8 mV and, as you can see \$C_{OSS}\$ rises to about 20,000 compared to about 5000 at 1V.

It's all relative and these could be farads, pico farads or fractions of femto farads.

So if the drain capacitance is 6 fF at 1V then it is likely to be in the realm of 24 fF at about 8 mV drain voltage. At 450 mV (as per the waveform in the question), the capacitance could be about 12 fF.

If 24 fF is charged with 10 uA the dV/dt will be 10 uA / 24 fF which is 417 volts per us OR 417 mV per nano second. Here's what it will look like against Sergei's picture (orange is the line I've added spanning between 6 ns and 7 ns and rising from 0 mV to ~417 mV): -

Clearly it's about the same sort of rate as he is seeing and the exponential asymtotic shape is going to be due to non-infinite drain resistance.

It's going to be more complex than this because the \$C_{OSS}\$ falls rapidly as drain voltage rises and, if the equivalent drain saturation resistance were infinite (i.e. a tending towards a true flat line), I would expect more like an exponential rise rather than a linear or asymtotic rise.

Anyway, @Mario, strip out anything you want and let me know to delete my answer.