# How does a CPU choose a path?

communicationcpudata

This is the most baffling question of all other concepts. I ask my teacher

"How does the computer choose a path?"

"They program it"

"How do they program it?"

"…"

I have a basic understanding of how a transistor works, how the CPU handles things, and the latter, but how does the CPU physically choose a path!? I want to learn the college level stuff, but google is not helping!!! All I get are these novice translations! Please help because I'm crying over not knowing the answer. Literally.

EDIT: I need a thorough answer explaining what is going on in the hardware please.

I'll make a brief attempt to explain the Datapath implementation, since it is a large topic.

CONTROL WORD : Control Word is basically the input code ( You can say, The master code) which controls what operation the computer will perform. A General control word will consist of an opcode, specifying a particular operation, like add or shift, followed by a few parameters like location of operands or the operand itself etc. In this figure, the control word wont be directly visible, so I have added another figure. Be careful, the second figure is not directly related to the first one.

Here a simple control word is shown.

---> DA stands for Destination and specifies the location where the result of computation will be stored.

---> AA and BA specify the location of operands A and B.

---> MB, MD are the Mux B and Mux D enable input (More on that later).

---> FS is the function select, and specifies what function the unit will perform.

Now back to figure 1.

---> A select and B select inputs are applied to Mux A and Mux B, which select the data inputs from the registers R0 through R3.

---> The input B is then passed to Mux b, to decide whether it is needed or not, because some operations only require a single operand, like shift and increment.

---> The A input and the output of Mux B ( which consists of either input B or a constant, as seen in the figure) is then applied to ALU. Note that B input is also applied to the shifter.

---> The opcode or Function select determines what operation will it be. At this point, the output of both the shifter and ALU is applied to Mux F, which selects whether it the output of ALU or Shifter which is needed. The Mux F select maybe a part of opcode.

---> Finally, the result passes through Mux D, and then it is applied to each of the registers for storage purposes. Which register to store in is decided by the And gates which enable Loading operation, with the address of the registers applied via decoder.

I hope this explains it.