How to use the newest version of VHDL in Vivado

vhdlvivado

The below code gives me an error hat i cant read from out object Q
Im sure newer version of VHDL supports it, how do i enable in Vivado does anyone know?
Before i used GHDL compiler with a flag option --use ieee=08
Or something similar to this

library IEEE;
use IEEE.Std_logic_1164.all;

--Non-gated SR latch, general configuration 2NORS
--Only works when using the new VHDL version

--Declare SR_Latch entity
entity SRLatch is
    port(
        clk: in std_logic;
        set : in std_logic:='0';
        reset : in std_logic:= '0';
        Q : out std_logic:='0';
        Q_n : out std_logic:='1'
    );
end SRLatch;


architecture behavioural of SRLatch is

begin
    process(clk) begin
            Q <= reset NOR Q_n;
            Q_n <= set NOR Q;
    end process;
end behavioural;

```

Best Answer

It never worked as far as I know. Not just in Vivado. Q is an output. You cannot read an output as you attempted with NOR. You can only write to it.

You could use inout, but this is dangerous. But best practice is to manipulate an internal signal and write that to Q.

But I believe you can set VHDL-2008 somewhere in the menu settings. Don't know about a syntactical way to do it though.

EDIT: It seems to be hiding in plain sight. It is set per source file in the "Source File Properties" window which is probably already open and just sitting in your regular layout in Vivado.

Also from the Vivado manual starting page 203:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf

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Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.

Electronic – Problem in synthesizing

Inside ringcounter, q3 is being assigned by both the concurrent assignment q3<='1' and DFF4. You can't have both at the same time.

Best Answer

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