LTspice Flip-Flop Troubleshooting – Common Issues and Fixes

flipflopltspicesimulation

I am trying to simulate a simple flip-flop in LTspice but I am having issues. I have followed some other similar posts but am not able to find why my flip-flop isn't outputting correctly:

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I'm no expert on LTspice's digital component models. But I can read the help, mostly.

It appears that the discussion Mike provides for LTspice suggests that unused pins are recognized by their digital compiler and their effects are removed (also any effects on delays, as well, if I'm reading correctly.) If I'm reading things correctly, leaving PRE and CLR unconnected means they are automatically removed as features of the DFLOP. That appears to be what you want. So I'd leave them unconnected and allow the digital compiler to do its magic.

If, however, you really want to apply direct signals to these lines, Mike writes that you do NOT want to ground them. That's because the digital compiler treats a direct connection to ground (which is always node '0' in the netlist) as telling the digital compiler to remove that pin and its effects. You can, however, apply a voltage source of \$0\:\text{V}\$, which won't be node '0' but will be named something else, entirely, and then the pin is kept by the compiler.

Finally, I believe that PRE and CLR are active-HIGH. This means to disable them you want to either leave them unconnected or else directly connected to ground in order to signal to the digital compiler to remove their feature additions. You don't want to connect them to \$5\:\text{V}\$! Given your pramaters, that means active. So the DFLOP won't be very responsive as a result.

You can verify a lot of this by looking in the examples\Educational sub-folder and find 160.ASC and load it up.

But I just wrote up an example to illustrate what I wrote above. I haven't used a DFLOP in LTspice before (at least that I recall now, anyway.) But it appears to work as I suggest. Have a look:

Note that I didn't change the voltage references to \$5\:\text{V}\$, instead using the default of \$1\:\text{V}\$ for the device. Also note that I took a clue from the example case and used a resistor and current source, instead of a voltage source. This has to do with "simulation issues." It's not strictly required. But if you create larger schematics, you will likely start to find this practice valuable because of the preference of Spice's algorithms for current sources (behavioral or otherwise) over voltage sources.

If you now add ground symbols and attach them to the PRE and CLR on the above schematic I wrote up, you will find it behaves exactly the same as before. The following does the same thing as shown above:

Related Solutions

D flip flop with asynchronous level triggered reset

The best answer for blocking vs non-blocking flip-flops assignment is already answered on Stack Overflow here. That answer also references to a paper by Cliff Cummings, here.

Now, the code for your second attempt will always result in with the behavior shown in the waveform, even with non-blocking assignments:

always @(posedge clock, rst)
begin
  if (rst) q <= 1'b0 ;
  else     q <= d ;
end

This is because the sensitivity list for signal rst is incorrect. The posedge keyword only applies to the signal immediately right of the keyword and not the following signals after the comma. @(posedge clock, rst) is equivalent to @(posedge clock, posedge rst, negedge rst). The else condition will be evaluated on the falling edged of rst, which is not desired.

A good linting, synthesizer, or LEC (logical equivalently check) tool should flag the dual edge trigger on rst as an issue; possible as a warning.

Electrical – Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop

The first one is not master-slave; you would have to cascade two copies of that circuit (with the clock inverted between them) to get the same functionality as the second circuit, which is indeed a master-slave (edge-triggered) flip-flop.

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Related Solutions

D flip flop with asynchronous level triggered reset

Electrical – Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop

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