System Generator: Does an fft block need a buffer

The error means that your design can not run as fast as you are telling the tools it needs to. There are a few possible strategies:

1. If you are doing this as an experiment without specific requirements, you could try a smaller divider, that is more likely to work at the clock frequency you have.

2. If your board allows you to select a different clock frequency for the FPGA, you can do that, and update the constraints with the lower frequency.

3. You can add registers to your design to reduce the length of the critical path, as described here.

4. You can add a clock divider to your design. There is an example in Pipelining and clock frequency issue.

Just a guess but looking at:

'C:\My Dropbox\Archivos sobre mi PFC\Files_Matlab\System Generator\Mis pruebas\bitstream\FFTv4*/*fftv4_cw.ise'

Note that '\' used in the majority of this line is the proper windows directory separator. The '/' used in the rest of the error and the stared bit above is not the correct directory separator for windows.

For instance this:

'C:/My Dropbox/Archivos sobre mi PFC/Files_Matlab/System Generator/Mis pruebas/bitstream/FFTv4/sysgen/fftv4_cw.ise'

is using the forward slash which isn't the windows directory separator.

As such I would venture a guess that there is an error somewhere in your project that set the directories incorrectly which is resulting in this exception.

It is possible that whatever library is doing this would accept either forward or backward but I doubt it, and very much doubt it would allow both versions in one path.

EDIT: Got that backwards fixed...