Usage of “safe” gated SR Latch

I just learned about SR Latches, D Latches, and their gated versions and I've got a little burning question.

So of course with the SR Latch, the professor told us that the "11" condition cannot occur because the circuit is unstable

_{(source: kfupm.edu.sa)}

Gated D Latch

Then, we learned about the D latch, which has a single input as opposed to 2, and eliminates the "11" condition from ever occurring.

But I realized at this point that in going from 2 inputs t0 1, the D latch also loses the ability to store a value while the clock signal is high because it will always be either "01" or "10" and setting or resetting.

So I was a little confused by that, what if the clock was connected and cycling over and over, and you wanted it to simply store the value? Why not a safe gated SR latch? So I just added some gates to the front to filter out the "11" condition.

So why isn't this used, or is it? Or how do memory elements that use this then store their value when clock is high? Our professor didn't mention this so I'm just curious.

"Safe" Gated SR Latch

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Safe Gated SR Latch