I was trying to convert from verilog netlist into a spice netlist using the option v2s
. Can I specify the pattern in which the ports will be arranged in my resulting spice netlist?
For example: if my verilog netlist is this:
F10L16B_NOR2X4 nor1 ( .o ( nor1_o ) , .i0 ( cnfg[0] ) , .i1 ( cnfg[1] ) , .VDD ( VDD ) , .VSS ( VSS ) );
and I wanted a corresponding spice netlist in this port order:
Xnor1 VDD VSS cnfg[0] cnfg[1] nor1_o F10L16B_NOR2X4
Best Answer
Since this question has been unanswered for a couple a of days now I am now posting the following slightly off-topic answer in the hope that it helps.
I don't know about v2s (I don't have access to hsim), but Yosys can also be used to convert Verilog to spice.
I don't suggest that you use Yosys (although I would find that awesome since I am the author of Yosys), I suggest that the v2s authors maybe had a similar approach to the problem as I had when I wrote my code.
Yosys defaults to alphabetical ordering of ports if no blackbox module for the cell is provided, but uses the ordering from the blackbox module if one is found.
So given the following input (as
test.v
)the command
yosys -p 'write_spice test.sp' test.v
will create the following output (astest.sp
).(The
blackbox
attribute is a specialty of Yosys. For most tools every empty module is a blackbox module.)For me this seems to be the most natural way to do that. Maybe you are lucky and the authors of v2s felt the same way..