Adding VHDL modules in ISE

fpgaise

I saw in some screenshots that people had VHDL modules inside another VHDL module at Sources Window in ISE Project Navigator. Every time I try to add new VHDL module (using RMB -> New Source…) it is created at the same hierarchy level as all others VHDL modules. Suppose that I make some complex component that consists of some simple components. Should I attach VHDL modules describing simpler components under the VHDL module describing complex component or should all modules be at the same level of hierarchy? I wonder because xxx.ucf file is always under the Top Module.

Best Answer

ISE sorts the hierarchy out for you. Once you've instantiated a lower block, it will appear under the top block, not at the same level of hierarchy.

Related Topic