Constraining unconstrained integer in record on use

vhdl

VHDL 2008 allows us to have unconstrained records. That is a record containing unconstrained vectors:

type dummy is record
    sample : unsigned;
    int    : integer;
end record;

when the record is used to define a signal one writes

signal s : dummy(sample(2 downto 0));

This procedure is handy if one wants to use records in port maps of entities with generic widths.

I like to use integers in some places since it is more convenient to write sig <= 4 than sig <= to_unsigned(4, sig'LENGTH). However if I do not constrain the integer, this might lead to to large types (wasted bits).

Is there a way to constrain these, post-definition, as well?

Best Answer

I'm not aware of any way to "post-constrain" an integer like that.

However, in my experience, the synthesis tools will take note of the source of the data that you write to any integer down the line (presumably irrespective of whether the integer is in a record or not, but I haven't tried it) and propagate any constraints from that source onto the destination.

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Your code doesn't compile, you can't use <= to assign to a variable. Nor can you assign to an input (which counter is defined as...)

You also can't have two separate processes writing to the same signal (when it's of a non-resolved type, like integer). Is this an academic exercise? Why not just have a single process which does:

if rising_edge(clk) then
  if up = '1' then
     count <= count + 1;
  elsif down = '1' then 
     count <= count - 1;
  end if;
end if;

As you have a limited range counter, you'll have to be explicit about making it wrap around (or saturate) when you try and increment it or decrement it beyond the acceptable range. The simulator will die otherwise. The synthesis tool may or may not do what you require, depending - but it's better to be explicit with that sort of behaviour.

Also, get rid of std_logic_arith - if you want vectors to be treated as numbers, use ieee.numeric_std.all instead

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Best Answer

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