Integer to std_logic type conversion

vhdl

I want to assign the value of a generic that is an integer to a signal which is a std_logic type. My generic can take only two values, 0 and 1.

How do I do that?

Many choices here. You can use a conditional signal assignment:

signal a:    std_logic;
signal int:    integer range 0 to 1;

a <= '0' when int = 0 else
     '1';

And the integer could be class constant, and derived from a generic.