What's the meaning of wire [a:b] c? Is it different from wire [b:a] c? or verilog considers them equal? Is there any syntax to convert different arrays to each other?
Electrical – Confusion over wire\array notatin in verilog
verilog
Related Solutions
A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values under a single name.
The difference between "[7:0] data" and "data[7:0]" is that the first is a single 8-bit-wide value while the second is eight single-bit values.
It's totally normal and useful to create an array of busses. They're sometimes called memories, because you can use them to model ROM or RAM. Your synthesis software can usually recognize when you've defined something that looks like ROM or RAM (for example, reg [7:0] data[1023:0] is basically 1K by 8-bit RAM) and synthesize it as actual physical ROM or RAM on the chip.
To understand which construct to use, just ask yourself what you have. Do you have a single multi-bit value? That's a bus. Do you have a bunch of single-bit values that you want to reference using a single name? Then use an array. Do you have a bunch of multi-bit values? Then use a memory.
Quartus by Altera has a free "web edition" that I've been using and linked earlier availvible for both Windows and Linux. It can build for a variety of FPGAs and then comes with a built in RTL viewer which is a good way to visualize you netlist. If the RTL viewer isn't enough, ModelSIM (which comes with Quartus) allows you to force inputs and simulate outputs.
Your example code compiles correctly and the built in RTL viewer shows the following image (an and gate):
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Best Answer
Verilog does not assume the Endianness of buses.
For example
In order to select the Most significant bit of C, you need to reference C[7]. While in order to to this for D, you need to reference D[0]
If you are trying to connect two busses together in Verilog they are connected MSB to MSB and LSB to LSB
So in the above example if we are trying to connect C and D together the LSB of C which is C[0] will be connected to the LSB of D which is D[7]
If C and D are not the same length
When you try to connect them together in Verilog they are connected starting from the LSB
In this case;
C : [7] [6] [5] [4] [3] [2] [1] [0]
...........................|....|....|....|
D : ....................[0] [1] [2] [3]
C[0] => D[3]
C[1] => D[2]
C[2] => D[1]
C[3] => D[0]
Well they are both multi-bit wires there is no difference between them
Just don't connect big-endian to little-endian unless you really mean to do this. Otherwise this might not give you the results you expect