flipfloplatch
So what is the difference between sr latch and level sensitive sr latch??
For sr latch, When 00, they just store the previous bit and when they are 01, the output q becomes 0, which they reset and when they are 10, the output q becomes 1, which they are set.
For example, if I have this level-sensitive sr latch:
how is the behavior different from the just regular SR latch??
The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.
An SR Latch will look like this
In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)
An SR Flip-Flop (also called gated or clocked SR latch) looks like this.
In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.
First a slight correction to your diagram. The NOT Q output is the output of the NOR1 gate, not the input you have shown.
When both inputs are LOW (0) the latch holds it state.
With S, R = 0, 0
If Q = 1, then NOR1 input is 0,1 and its output (NOT Q) is 0 keeping Q = 1 If Q = 0, then NOR1 input is 0,0 and its output (NOT Q) is 1 keeping Q = 0
i.e. NO CHANGE
If S = 1 (R = 0) then the output of NOR1 (NOT Q) will be 0 and the output of NOR2 (Q) will be 1 - the latch is SET, Q is HIGH
If R = 1 (S = 0) then the output of NOR2 (Q) will be 0 and the output of NOR1 (NOT Q) will be 1 - the latch is RESET, Q is LOW
The problem comes when both S and R inputs are taken HIGH at the same time and forms a race condition. This logical condition (S = 1, R = 1) is to be avoided as the output cannot be determined.
Best Answer
There is only level sensitive or gated SR latch's. The other type of latch is edge triggered, also known as a flip-flop. Your diagram shows a SR latch with gated inputs.
In other words it can be set or cleared only if C (the gate control) is true and either S or R are true. If S & R are true and C becomes false, the output is unpredictable. A more simple SR latch would be just the 2 nor gates, using S1 and R1 as inputs, but other logic needs to make sure either S1 or R1 is false at all times. They are level sensitive in that the logic driving them must maintain a 'level or continous state until it is time to change.
By adding another gate to C input and tying it to the outputs you have a flip-flop, which trigger only on the rising or falling edge, yet still has S and R inputs to use if needed. Once the edge is detected, they maintain state until the next change using a rising or falling edge. Check this link for some details on the RS latch, as well as Wikipedia for flip-flops and 'D' latchs, which are used a great deal in many digital circuits.
Part numbers to look up for details:74HC02 nor gate, 74HC74 flip-flop, 74HC573 latch.
https://www.youtube.com/watch?v=VtVIDgilwlA