Electrical – The method to get synchronous D-flip flop with three inputs,D,CLK and reset

flipflop

I want a synchronous D-flip flop with three input,reset,D and CLK,but i can't find it,only four or two inputs,and four inputs just D,CLK,Set and reset ,but find the asynchronous D-flip flop with three input on the Internet.

Can i do anything to let asynchronous D-flip flop become synchronous D-flip flop ? For example,change NAND by AND .

Someone told me : take the 4 input one and ignore the set, that is, hold it false and remove any following logic that no longer changes state as a result,but i don't know last sentence meaning and the method.

Best Answer

Just take a CD4013, or whatever series you're working with, and pull the set pin low.

From: TI Datasheet

Edit: Also from the datasheet:

A high level at the SET or RESET inputs sets or resets the outputs, regardless of the levels of the other inputs. When SET and RESET are inactive (low), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The resistor and capacitor at the RESET pin are optional. If they are not used, the RESET and SET pin must be connected directly to ground to be inactive.

Related Solutions

Electronic – Is making a D flip flop with asynchronous level triggered reset possible

Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset":

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q <= 1’b0;
        else
            Q <= D;
    end

(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.

Electronic – Flip flop with load/set, reset, clk, and input

You've been looking at incorrect components: D type flip-flop is used to sample the D input on each clock cycle, but you want to use load signal in order to enable sampling. Please note that the signal set which you wanted to use as load has different funtionality - it causes the output to go high (regardless of the value of D).

What you are looking for is D Flip-Flop with Enable. There are two simple approaches to add this functionality to a regular D-FF.

Feedback:

Adding a MUX which is controlled by Enable signal. On each clock edge the flop will either sample the new value, or the old value (which is equivalent to keeping an old value).

enter image description here

Clock gating:

Instead of MUXing the input to the flip-flop, you may simply disable the clock when you do not want to sample a new value. This approach is widely employed in order to reduce the power consumption (no clock -> no activity -> no active power consumed).

As pointed out by @Supercat in the comments, clock gating is the more sophisticated technique which requires a bit more expertise because it presents additional delays in clock path.