Analog CMOS layout finger size
I am doing analog CMOS layout in under 65nm processes.
What is the "rule" on the finger size I use for layout? Is there a rule of thumb for this?
For example, say I have a simple 2 stage opamp with an NMOS differential pair with PMOS active load and a second stage which is a common source stage. So I have three stacks to layout – a PMOS stack, and two NMOS stacks if you include the biasing for the NMOS differential pair.
You have a total width of a transistor but you can have transistor fingers each with their own width and then the amount of fingers*finger width = total width. So how to pick the finger width is the question.
Best Answer
Go for convenient sizes, that you can interdigitate to get thermal matching and implant matching.
Also keep the surrounding structures (wells, active, metal) identical for FETs you need to match.
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How to pick the actual finger width (say W/L = 100/0.5)?
Determine how you want/need to pack the circuit into available space.
If no space constraint, you should still use multiple stripes because sharing drains will reduce the parasitic capacitance, and give you a free Bandwidth boost.