Electronic – Difference between >> and >>> in verilog

data-operatorsystem-verilogverilog

What is the difference between >> and >>> in verilog/system verilog? I know that == tests for only 1 and 0, while === tests for 1, 0, X, Z. So how is that similar to the shift operator?

Best Answer

It is not similar to ==/===, if the left hand operand is signed then >>> performs sign extension.

reg signed [9:0] b = 10'sb11_0101_0101;
reg signed [9:0] a_signed;
reg        [9:0] a_unsigned; 

always_comb begin
  a_signed   = b >>> 2;
  a_unsigned = b >>  2;
end

Result:

#a_signed   1111010101
#a_unsigned 0011010101

Example on EDA Playground.

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