Electronic – Half Precision Floating Point in Systemverilog

system-verilogverilog

I have a 16 bit vector defined as:

logic [15:0] x;

In my simulation I want to assign x a half precision floating point number.
For example: 7.42

Is there a simple way to do it ?

Best Answer

you can do binary and decimal arithmetic's, but fixpoint or even floating point, you need to program all yourself, or search for a existing free implementation.

When it is only about a testbench, most commercial simulators allow to integrate with C or SystemC. Here you can do all the floating point stuff you want (e.g. I used to check my verilog algorithms like CRC with a C/C++ implementation)

Edit: if you have access, you might try a high level systhesis tool. I once tried Xilinx HLS with some complex integer Algorithm and was impressed by the result. Maybe they also can do floating Point stuff. Never tried that myself...

Another idea: on github or opencores you will find verilog floating point implementations (or complete FPU's)

Related Solutions

Electronic – SystemVerilog: How to give different parameters to modules in the same array

Use a generate loop

for(genvar ii=0; ii<4; ii++) begin : counter_loop
  my_counter #(.INIT_VALUE(ii)) my_cnt (.clock, .reset ... );
end : counter_loop

If the values you want to override cannot be computed by a simple loop expression, you can use a parameter array.

parameter int ARRAY_VALUE[4] = {1,3,5,10};
for(genvar ii=0; ii<4; ii++) begin : counter_loop
    my_counter #(.INIT_VALUE(ARRAY_VALUE[ii])) my_cnt (.clock, .reset ... );
end : counter_loop

Electronic – SystemVerilog: Sensitivity list of always_comb

Because simulation does not do the same kind of data flow analysis that a synthesis tool does to know that b is just a temporary variable. The LRM was written thinking that you always write to variables before reading the same variable in the same block. An always_comb block should be written as if it were a function called whenever an input to the block changes. To have the block re-trigger can be very bad for performance.

The same style is used for a sequential always_ff block: a read before write within the same block is a flop, a write before read is a temporary variable.

Best Answer

Related Solutions

Electronic – SystemVerilog: How to give different parameters to modules in the same array

Electronic – SystemVerilog: Sensitivity list of always_comb

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