digital-logicflipflop
I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in Q and Q′.
However, both R and S require input from the other's output, and the other's output requires input from the other other's output. What comes first the chicken or the egg??
When you first plug this circuit in, how does it get started?
There is certainly a lot of stuff taught in school that is not required in the job market. And, of course, there is a lot that is not taught that should be. This could probably be said about any job market, since it depends on what specialty the person ends up being employed in. Unfortunately for you, neither your professors or I can tell you what you will and will not use once you get a real job in your field.
For example, I don't use calculus in my job as an E.E.. But a coworker, who is also technically an E.E., uses calculus almost daily. I design PCB's and FPGA's, while he writes DSP algorithms. There was no way our teachers could have ever known what we needed to get the job done.
That being said... Your question to your teacher, about the initial value of the latch or Flip Flop (FF), was a great question and the way your professor responded shows her ignorance of the requirements for designing practical digital logic circuits.
Simply put, the initial value of a Latch or FF is indeterminate. Meaning, it will have an initial value but you won't know what it is in advance. A given latch/FF might even have different initial values from one power-up to the next. Sometimes it'll be a '0', other times a '1'. Things like temperature and how fast the power rails ramp up will effect the initial value.
If your circuit requires a known initial value then you must force the value. Normally this is done using some sort of set/reset/clear input that is driven by a reset signal. This is also why almost any digital circuit of reasonable complexity has a reset signal. Reset signals are not just for CPU's.
They start out undefined, that is they could be set to either.
When you switch power on, assuming a real latch with no input signals, both gates will want to output high. However due to no two gates being exactly the same (and other real world effects), one will "win" the race to bring it's output high first, and set the others output to low. The same gate may not win every time, so you can't predict the state at power on.
This diagram (from the second link below) helps to visulalise things:
For further reading about this and metastability, see these links:
Wikibooks SR latch
Latches and FFs
Wiki Metastability
Metastability document
Best Answer
A perceptive question. In fact, if you build this latch in a simulation program, it will indeed show you that it can't predict what state it will start in:
But if you set one of the inputs high (those are pushbuttons on the left), the signal will propagate through (remember, 1 OR [anything] equals 1) and the circuit will latch that state:
These are NOR gates, so the inverted output goes low when either input is high. The program I used is Logisim. It is small, and I recommend it for starting out. Logic compilers (FPGA and everything else) love to complain about uninitialized states. This was a great first example.
Now, I know that in real life, the circuit will randomly latch into one or the other state on its own. Many others have pointed that out. But sometimes, it's important that it reliably start in one state or another, and that's what all the warnings are about.