In Altium Designer 14.3 I am trying to merge two 16bit buses into a 32bit bus with one of the input buses becoming the lower 16 bits and the other the upper 16bits of the output bus. Below is an image if my attempted method.
When I try and compile the document I receive the following error:
Duplicate Net Names Bus Slice \Y[31..0]. I get how Altium thinks that I am trying to redefine the
\Y net however I don't see a better way to merge the two buses together other than breaking out all the pins of the separate two buses and merging them together. This is how I would do the design if it were a FPGA HDL schematic.
How should I do this?
I ran into the same problem, and I solved it by changing the local net name in the subsheet so that it doesn't match the port name. Below is an example of what I did: