Electrical – Design Asynchronous State Machine using T flip-flop

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There is this question that i don't really get the solution:

Design a pulse-mode circuit having two input lines x1 and x2, and one output line z. The circuit should produce an output pulse coincide with the last input pulse in the sequence x1-x2-x2. No other input sequence should produce an output pulse.
Use T-FF: T = 1, C acts as input

this is the solution that the book gives:

First, I don't really get the part in step 4 and 5 where do they get the table with Transition and C?

second,I don't really understand step 6 where you implement the equation, Why do we have to use negative edge triggered T flip-flop? why not positive edge triggered T flip-flop?

thank you in advance 🙂

Best Answer

OK, I hope this helps. I think the confusion for C1,C2 comes from going directly from the state diagram to the Karnaugh map. Here is a state table showing how you go from one state to the next.

Notice from state B(01) X1 causes the machine to go to A(00). That means [C1,C2] must be [0,1]. Only Y2 must toggle. From B(01) X2 causes the machine to go to C(10). This means [C1,C2] must be [1,1]. The both must toggle. Form this table you should be able to see how the values of C1 and C2 are determined. Now If you take the C1 columns and put them together you get the C1 Karnaugh map from the answer. Similarly put the C2 columns together to get the C2 Karnaugh map.

Related Solutions

Difference between rising edge falling edge D flip flop (asynchronous reset)

The only change that is required to convert your falling-edge triggered flip-flop to a rising-edge triggered flip-flop is to swap the true (non-inverted) clock and the inverted clock at the pins of your tri-state buffers and the transmission gate. For example, the center transmission gate in a rising-edge triggered flip-flop would have the true clock connected to the NMOS transistor and the inverted clock connected to the PMOS transistor.

By the way, near the middle left of your diagram you have a circled inverter that shows Q at its output and !Q at its input. That's correct...the output of the inverter just to the right of the circled inverter is !Q (Q-bar) rather than Q. If you follow the path from the D input through an inverting tristate buffer and the NOR gate you will see that the signal at the right end of the (non-inverting) transmission gate must have the same polarity as D, so that point in your circuit represents the true (non-inverted) Q value.

D flip flop with asynchronous level triggered reset

The best answer for blocking vs non-blocking flip-flops assignment is already answered on Stack Overflow here. That answer also references to a paper by Cliff Cummings, here.

Now, the code for your second attempt will always result in with the behavior shown in the waveform, even with non-blocking assignments:

always @(posedge clock, rst)
begin
  if (rst) q <= 1'b0 ;
  else     q <= d ;
end

This is because the sensitivity list for signal rst is incorrect. The posedge keyword only applies to the signal immediately right of the keyword and not the following signals after the comma. @(posedge clock, rst) is equivalent to @(posedge clock, posedge rst, negedge rst). The else condition will be evaluated on the falling edged of rst, which is not desired.

A good linting, synthesizer, or LEC (logical equivalently check) tool should flag the dual edge trigger on rst as an issue; possible as a warning.

Best Answer

Related Solutions

Difference between rising edge falling edge D flip flop (asynchronous reset)

D flip flop with asynchronous level triggered reset

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